1. Field of the Invention
The present invention relates to a digital data multiplex communication system, particularly to a pulse stuffing multiplex communication system utilizing a stuffing technique.
2. Description of the Prior Art
Conventionally, multiplexing of digital signals has been carried out by a time-division multiplex system. If the signals to be multiplexed are asynchronous digital signals, then a pulse stuffing multiplex technique has been utilized.
Generally, according to this type of multiplex communication system, the positional relationship between a writing clock and a reading clock for the memory is monitored for each interval of m clock bits at the transmitting side to insert stuffing bits as the phase difference between both clocks is reduced to within predetermined j-bits (j.ltoreq.m).
FIG. 1 is a view illustrating an example of an arrangement of a pulse stuffing circuit for a single channel for the above prior art. Here, for the sake of clarifying the description, a case in which a single channel signal of low order data signals is synchronized with a high order frequency is referred to. Low order data signal Ii is entered to m-bit memory circuit 5 from terminal 1 to be stored therein by using a writing clock signal obtained from l/m frequency divider 6 which divides low order clock signal CLi entered from terminal 2. This data is read out from m-bit memory circuit 5 by using a clock signal obtained by l/m frequency divider 7 which divides clock signal CL.sub.H entered in it. The data is emitted from terminal 4 as high order data signal Hi. By monitoring the phase difference between the S-th (s.ltoreq.m) divides outputs of each of frequency divides 6 and 7, phase comparator 8, when the difference is reduced to within the predetermined j-bits, emits clock control signal 10. While clock control signal 10 is being entered, clock signal control circuit 9 suppresses the clock at the higher order side. FIG. 2 is an example of a timing chart illustrating the relationship between the signals when m=8 and S=8. In other words, each bit Ai of low order data signal Ii is sequentially written into eight-bit memory circuit 5 by the clock from divider 6, which divides low order clock signal CLi to 1/8. On the other hand, high order data signal bit Ai is sequentially read out from eight-bit memory circuit 5 by the clock emitted from frequency divider 7, which divides high order clock signal CL.sub.H. When, by monitoring the phase difference between the low and high order data signals, it is found that the phase difference has been reduced within a predetermined interval, phase comparator 8 emits clock control signal 10, and high order clock signal CL.sub.H is suppressed. Accordingly, while clock control signal 10 is being emitted, reading of high order data signal Hi is stopped and a corresponding number of stuffing bits is inserted into this vacant data position by a multiplexer circuit (not shown) in the subsequent process. For all other channels, a similar operation is conducted as well, and these high order data signals synchronized for all channels are multiplexed at the multiplexer circuit to be fed out.
In the above conventional embodiment, as the difference between the low order frequency and the high order frequency becomes greater, the operating range of the phase difference between the writing and reading clock signals greatly fluctuates. Then, if the phase difference is sampled and monitored at the memory bit cycle, the number of sampling cycles repeated in a single frame of the high order data cannot be an integer. Therefore, the minimum phase difference between the writing clock and the reading clock signals cannot be detected, with the result that the reading clock signal overtakes the writing clock signal. Then, if all the bits are to be monitored, the size of the pulse stuffing circuit becomes large and complicated, thereby increasing the power consumption.